This invention relates in general to video electronics, and in particular to a high speed video display memory using dynamic memory cells implemented on the same chip as the video display controller.
A typical computer system includes a video card that carries the circuitry for processing video signals and for driving the display panel. FIG. 1 shows a conventional video card 100 that includes a display memory chip 102 (sometimes referred to as a frame buffer) connected to a controller chip 104 via input/output (I/O) pins 106. Display memory 102 stores data that represent the color or intensity of light for every picture cell (pixel) on the video screen, and controller 104 processes the data and drives the display. A drawback of this type of system is limited bandwidth between the memory and the controller caused by the limited number of data input/output pins 106 on the two chips.
It is desirable to substantially increase the rate of data transfer between the video memory and the video processor. Using a memory system with multiple banks improves the bandwidth somewhat. For example, dual-bank video memories have been developed whereby two word lines one from each bank can be selected at the same time. While some improvement is achieved by this design, still higher bandwidths are required.
Integrating both the memory circuit and the controller on the same chip is a solution that promises a significant increase in the bandwidth. With the memory on the same chip as the processor, instead of e.g., 32 bits over 32 I/O pins, 128 or 256 bits can be accessed internally at very high speeds.